Generally, a semiconductor device (also called a device) manufactured by a predetermined assembly process of a semiconductor fabrication process experiences a test process for determining whether or not a specific function is finally carried out.
FIG. 1 is a perspective view illustrating a system for testing a semiconductor device. Referring to FIG. 1, the system for testing the semiconductor device includes a test head 2, a handler 3, and a HIFIX board 1. The test head 2 tests a semiconductor device. The handler 3 carries a predetermined number of semiconductor devices, performs a desired test on the semiconductor devices, classifies the semiconductor devices according to their grades, and loads the classified semiconductor devices thereon. The HIFIX board 1 is located between the test head 2 and the handler 3, such that it establishes an electrical connection between the semiconductor devices and the test head 2. In other words, where the semiconductor devices seated in an insert on a test tray are brought into contact with sockets of an (m×n) matrix on the HIFIX board 1 on the condition that the HIFIX board 1 having the sockets of the (m×n) matrix is matched with a test site of the handler 3, the semiconductor test system may simultaneously test (m×n) semiconductor devices.
FIG. 2 is a schematic diagram illustrating a connection structure between a test head and a HIFIX board of a semiconductor device test system. FIG. 3 is another schematic diagram illustrating a connection structure between a test head and a HIFIX board of a semiconductor device test system. Referring to FIGS. 2 and 3, a HIFIX board of a semiconductor device test system generally includes a socket board 10 and a bundle 20 of coaxial cables. In the above-mentioned structure, a test socket 12 in which a device under test (DUT) (i.e., a Ball Grid Array (BGA)—type DUT) 40 is inserted, is mounted on one side of the socket board 10. A HIFIX-board connector 14 connected to a relay connector 22 of the HIFIX board of the coaxial-cable bundle 20 for a relay purpose is mounted on the other side of the socket board 10. The coaxial-cable bundle 20 includes a relay-purposed coaxial cable 23, the first relay-purposed connector 22 of the HIFIX board, a second relay-purposed connector 24 of the test head, a first support frame 21 for supporting the first connector 22, and a second support frame 25 for supporting the second connector 24. In this case, the first connector 22 and the second connector 24 are installed on both sides of the relay-purposed coaxial cable 23, such that the first connector 22 is connected to the HIFIX-board connector 14 and the second connector 24 is connected to a test-head connector 35.
In the meantime, a test head device includes a test head substrate 30 and a variety of circuit elements loaded on one or both sides of the test head substrate 30. For example, the test head may include an algorithm pattern generator (ALPG) chip 31, a driver chip 32, a comparator chip 34, an interface chip 33, and the test head connector 35. The ALPG chip 31 may have unique characteristics which are classified according to individual semiconductor test system manufacturing companies. The driver chip 32 records a memory test pattern generated from the ALPG chip 31 in the DUT 40. The comparator chip 34 compares a level of the signal read by the DUT 40 with a predetermined reference value. The interface chip 33 controls a control computer (not shown) to interface with the ALPG chip 31. The test head connector 35 connects the second relay-purposed connector 24 of the test head to the test head substrate 30. Generally, the driver chip 32 or the comparator chip 34 may be implemented with a separate analog IC or ASIC. The reference number 36 is a control-purposed connection terminal for connecting the control computer to the test head substrate 30. The reference number 37 is a power-supply connection terminal.
FIG. 4 is a conceptual diagram illustrating a scheme for cooling a test head of a semiconductor device test system. As shown in FIG. 4, with reference to FIG. 2, in order to cool a test head, water or liquid cooled by a chiller 50 located outside of the semiconductor device test system encircles the surrounding of a test head substrate via pipes 52, such that the cooling of the test head may be carried out.
In the above-mentioned semiconductor test head, a driver chip or a comparator chip is implemented with an analog IC such that the size of the semiconductor test head is large and only one channel is assigned to a single IC. However, the above-mentioned semiconductor test head generally requires at least 30 channels to test only one DUT, and thus require several tens of driver chips and several tens of comparator chips according to the number of channels, such that it is difficult for the driver chips and the comparator chips to be physically mounted on one test head substrate. In addition, the above-mentioned semiconductor test head uses a large number of expensive analog ICs, such that the system including the test head becomes expensive. Furthermore, with the increasing demands of a handler capable of simultaneously handling a plurality of DUTs, a variety of improved handlers capable of simultaneously handling 512 DUTs have recently been developed and come into the market, such that a total of 15360 ICs (=30×512) are generally needed for a minimum of 30 channels on the condition that the minimum of 30 channels are used to test one DUT. As a result, a test head substrate has become be wider and longer, the complexity of mounting the individual ICs on the test head substrate has become higher, a higher-performance chiller has been needed, difficulty of pipe installation has increased, and a signal distortion (i.e., skew) among the ICs has become more serious.